# Physical Methods of Speed-Independent Module Design \english\

Consider an algorithm of operation for interface circuitry realizing speed-independent four-cycle signalling convention (FCSC). In

## Physical Methods of Speed-Independent Module Design \english\

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to three components:

(i) CLi is the load capacitance of the i-th gate;

(ii) Cpsi is the power supply bus capacitance associated with the i-th gate;

(iii) Cin is the input capacitance of the OVD circuit.

Let pi is a probability of the i-th gate being in the state of high output potential. In this state the capacitance CLi is connected with power supply bus through the low channel resistance of turned-on transistors in PMOS network of the i-th gate. Then equivalent capacitance Ceq connected to the OVD circuit input equals

(7)

where N is a number of gates in the considered SPP. Here the resistance of conducting PMOS network is assumed to be negligible.

Equation (7) is also true for CL including several SPPs. In that case summing must be carried out for all the gates belonging to CL.

Simulation shows that ton and toff are proportional to the OVD time constant =R1Ceq. It was also obtained that when N>20, the component under the sign of summation in Equation (7) can be much larger than the component Cin. Due to voltage drop V the effective power supply voltage is reduced and CL performance is decreased by about 35 percent .

In order to make SIM operating faster special attention must be paid to reducing the capacitance introduced by CL.

The simplest case of CL is a scheme degenerated into a set of wires called a multi-bit bus. Let us develop the OVD circuit for such a CL.

Multi-bit bus consists of several lines. Each line can be considered as a medium for signal propagating from one end of the chip to another. Delay of signal propagation through a line depends on several factors:

(a) output impedance and symmetry of driver circuit;

(b) initial state of the line: if driver is symmetrical, line switching from high to low voltage lasts shorter than reverse switching;

(c) electrical properties of the line as a signal propagation medium (resistance of conducting layer and capacitances between the line and other wires next to it);

(d) length of the line;

(e) input impedance and sensitivity of receiving circuit.

Since different lines of the bus operate in different conditions (a)-(e), signal propagation delays are different, too. From the standpoint of environment the bus behaves like any other more complicated CL.

Asynchronous RAM designers use a bus transition detector since 1980s [13-15]. Such a detector is usually based on double-rail address coding and two series connected transistors for each address bit . One of the transistors receives the true address signal and the other receives the complementary address signal of the particular address bit. For any steady state condition one of the transistors will be turned on and one will be turned off. There will be a finite rise and fall time during a transition of the address bit. There is a short time during which both transistors are conducting. The establishment of the conductive path provides the detection of the address transition. In the first asynchronous RAMs the output signal of the transition detector is used for bit line precharging and for enabling/disabling sense amplifiers and peripheral circuitry.

Self-timed RAM announced in 1983  used transition detectors not for address transition only but also for detecting read/write completion and address/bit line precharge completion as well.

The CMOS transition detector was invented in 1986 . This circuit is also based on double-rail coding and uses a pair of series-connected NMOS transistors (Fig.12). The scheme for n-bit bus control contains n line transition detectors (LTDs) and n AND-gates. Outputs of AND-gates are united in node M forming wired OR. The output inverter serves as a pulse shaper. Capacitors C1 and C2 are intended to prolong rise time of the LTD output signal (true and complementary). This is necessary for reliable detection.

The main drawback of the circuit is speed dependence. One can see that if true and complementary address bit signal have different propagation delays, the conducting path via NMOS transistors will never be formed.

Using the OVD circuit proposed in Section 4.2 as LTD we can avoid this drawback.

Note that address transmission through the address bus is unidirectional. So to detect completion of bus transition it is enough to recognize the bus state at the destination end. For this purpose we modify CL to consist of n lines. The modification means introducing n LTDs, each actually a CMOS inverter chain. Each chain contains two inverters loaded with a capacitance (Fig.13). Input of each LTD is connected with corresponding line of the bus at the destination end. Power supply pads of all LTDs are connected to the current input of the same OVD circuit.

The parameters of the input current signal for the OVD circuit are varied by

(i) value of capacitances C1 and C2 ;

(ii) dimensions of MOS transistors M1 -M4 .

Since all transitions in CL are of the same duration and can be lengthened to be outlast the OVD turning-on time, we simplify the interface circuitry by disallowing the asymmetrical delay.

Due to short duration of normal transition in this CL we must take into account the integral nature of the sensitivity of the OVD circuit. OVD sensitivity depends on both amplitude and width of input current pulse. Simulated operation region of the OVD circuit for current pulses shorter than 30ns is shown in Fig.14. It is obvious that in this case the threshold of the OVD circuit must be determined by threshold charge Qth value. The OVD input charge Q equals to where I is OVD input current, t is a moment of time when transition occurs, w is a width of input current pulse. Turning-on condition for the OVD circuit is Q=Qth.

When the LTD circuit shown in Fig.13 is used, the charge value Q is determined by either C1 or C2. Namely, if the line goes from low to high voltage, Q=VC2. If the line goes in the reverse direction then where V is charging/discharging voltage, approximately equal to the effective power supply voltage: VVdd -V. Here Vdd is OVD power supply voltage and V is CVC voltage drop.

The OVD circuit with typical parameters (See Table 1) has a threshold charge value Qth =4.010-12 C. When C1 =C2 =CL , the minimal value of CL providing OVD capacity for operation is about 1.010-12 F.

Influence of transistors M1 -M4 dimensions on LTD delay d is determined by approximation :

where ~ is a sign of proportionality, Gn and Gp are the conductances of NMOS and PMOS transistors respectively (CL =C1 =C2.)

Since and where W and L are width and length of transistor channels of the corresponding conduction type, the LTD delay d is proportional to .

It has been obtained that for , , CL=1.0pF and Vdd-V=5.0V the LTD delay d=7.6ns.

When LTD works jointly with the OVD in the speed-independent bus, the real value of the LTD delay will increase by 30-40 percent due to OVD's R1 effect on the effective power supply voltage.

To determine the appropriate value of R1 in the OVD circuit we must know threshold input current Ith corresponding to threshold voltage drop Vth recommended to be equal to 400mV.

Average input current Iav in transient state of one line is determined by the expression Iav =CLv where v is the average rate of increase in the output signal for an inverter included in LTD. For typical values v=1.0109 Volts per second and CL =1.0pF, Iav =1.0mA. Accepting Ith =0.4mA and Imax=2.0mA we obtain R1=1k and rb=100.

Simulation has shown that in this case OVD turning-on delay can be approximated by an empirical expression:

ton[ns]=8.1+0.1n

where n is the address bus bit capacity. Total delay of recognizing address transition ttot =dg+ton where g is a coefficient of the LTD delay increase due to reducing power supply voltage. As we showed above g1.35. It can be seen that if n=32, ttot=21.6ns.