Physical Methods of Speed-Independent Module Design \english\

Consider an algorithm of operation for interface circuitry realizing speed-independent four-cycle signalling convention (FCSC). In

Physical Methods of Speed-Independent Module Design \english\

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on of CMOS CL for output validity detection was proposed in 1990 [7]. Contrary to the method of EMR detection this one is based on introducing direct coupling of source and receiver. While CL is in steady state it consumes current of about 10-9-10-8A which does not allow OVD switching. The interface circuitry gets information on CL output validity and in turn informs the environment about CL readiness to input data processing. When an input data arrives CL changes its state to "transient", current consumption increases to 10-4-10-2A, which switches the OVD, thus informing the interface circuitry about output invalidity. The latter lets the environment know about CL business.

After the computations in the CL are finished, the current consumption decreases down to the steady state value, and the OVD sends a signal of output validity.

 

4.1 Information carrying signal

 

Current consumption by CMOS CL contains useful information on CL state. CMOS CL is a network of CMOS gates, so the current consumed by CL is a superposition of currents consumed by CMOS gates included in the CL. Each CMOS gate contains PMOS transistor and NMOS transistor networks (Fig.5). While a gate is in a steady state either the PMOS or the NMOS network is in a conducting mode. When a gate switches the non-conducting transistor network becomes conducting. There is usually a short period in switching time when both networks are in a conducting mode.

 

 

Generally, current consumed by a CMOS gate includes three components [9,10]:

(a) leakage current Ilk passing between power supply and ground due to finite resistance of non-conducting transistor network;

(b) short-circuit current Isc flowing while both networks are in a conducting mode;

(c) load capacitance CL charge current ILC flowing while a CMOS gate is switching from low to high output voltage via conducting PMOS network and CL .

SPICE simulation has shown [5] that amplitude of current consumed by a typical CMOS inverter depends on CL and is limited by the non-zero resistance of the conducting PMOS network (Fig.7). The integral of consumed current is proportional to CL . When a gate switches from high to low output voltage, the component ILC is negative by direction and negligible by value (Fig.7b). It is evident, the switchings from high to low output voltage occur at the expense of energy accumulated in CL during the previous switching from low to high output voltage. The component Isc does not depend on direction in which a gate switches.

 

 

The component ILC equals to ILC = CLVdd f where Vdd is a power supply voltage, f is a gate switching frequency. Veendrick has investigated the component Isc dependencies on CL and rise-fall time of input potential signal [10]. He showed that if both input and output signal have the same rise-fall time, the component Isc cannot be more than 20 percent of summary current consumption [10]. However, when the output signal rise-fall time is less than input one, the component Isc can be of the same order of magnitude as ILC. In that case it must be taken into account. As to the component Ilk, it entirely depends on CMOS process parameters and for state of the art CMOS devices Ilk is about 10-15 -10-12 A.

So, the analysis of CMOS gate current consumption allows us to conclude that in transient state a CMOS gate consumes a current I= Ilk+Isc+ILC and in steady state it consumes only Ilk<< I . The difference between two states from the viewpoint of current consumption is several orders of magnitude. So, CMOS gate output validity detection is possible, both in principle and in practice.

In Section 2 we presented series-parallel model of computations in CL. We showed that in every moment during switching current consumed by CL is a superposition of the currents consumed on the activated signal propagation paths (SPPs). Now, considering CL implemented by CMOS devices we should note that while logical signal propagates through SPP the neighbouring gates switch in opposite directions. That is why a curve of current consumed by a ten inverter chain (Fig.8) looks like a combination of crests and troughs. Nevertheless, in the very lowest point of the curve the current consumed by CL in a transient state remains several orders more than in a steady state.

 

 

4.2 OVD implementation

 

The proposed OVD circuit, shown in Fig.9, is a threshold circuit translating an analog current signal I into a logical signal OV.

The OVD circuit contains a current-to-voltage converter (CVC) consisting of the resistor R1 and the diode D1. The OVD also contains a comparator implemented by the MOS transistors M1-M7 and resistors R2,,,R3 . CMOS CL consumes the current I and introduces a capacitance Cin . The capacitance Cout represents the load caused by the interface circuitry. A low potential output signal of OVD corresponds to CL output validity. A high potential output signal corresponds to CL output invalidity. So, OVD generates OV signal in negative logic manner.

The transfer characteristics of CVC is determined by a system of three equations:

 

where I is an input current of CVC, V is a voltage drop on the CVC circuit, Ir is a current flowing through the resistor R1, Id is a current passing through the diode D1, I0 is a leakage current of the diode, rb is a bulk resistance of the diode. Here stands for kT/q where k is Boltzmann's constant, T is absolute temperature, q is charge of an electron.

Equations (1)-(3) determine the functional connection F between input current I and voltage drop V: . Graphic solution of the system is shown in Fig.10.

CVC parameters to be calculated are R1 and rb. Initial data for calculating R1 are the threshold voltage drop Vth and corresponding threshold input current Ith . Value Ith is determined by minimal current consumed by CMOS CL in transient state. Initial data for calculating rb are maximal voltage drop Vmax and corresponding maximal input current Imax. Value Imax is determined by the maximal number of gates in CL switching simultaneously and their load capacitances.

The comparator chosen is the CMOS ECL receiver proposed by Chappell et al.[11]. The circuit includes a single differential amplifier stage with built-in compensation for parameter variations, followed by a CMOS inverter. The comparator has 100-mV worst-case sensitivity in 1-m technology. Detailed static and dynamic analysis of the comparator circuit was given in [11].

The comparator compares input voltage signal Vin with reference voltage Vref. If Vin <Vref the comparator output signal equals to logical zero which means that CL outputs are valid. Otherwise, Vin >Vref, the comparator output signal equals to logical "one" which means that the outputs are invalid.

As it follows from the OVD circuit configuration,

 

where Vdd is a voltage of power supply.

Equations (4) and (5) allow us to calculate the threshold voltage drop V of the CVC circuit:

since , so

If 0<V<500mV then the diode D1 of CVC operates in the very small current region Id 0 and Id <<Ir. So the component Id in the Equation (1) can be neglected and IIr =V/R1 .

For practical values of the threshold input current of the OVD circuit is reversely proportional to the resistance of R1 : . Substituting Equation (6) yields

.

As to choosing value of rb it must be done with regard to maximal voltage drop Vmax .

If V>750mV, the diode D1 is in active mode and while rb <<R1 the condition Ir <<Id is true. So, in the large current region IId and Equation (2) determines an almost linear dependence between I and V. For instance, if the maximal voltage drop Vmax =900mV and maximal input current Imax=2mA, then in accordance with the Equation (2) rb 100. Typical element values for the OVD circuit with Vth =400mV are given in Table 1.

 

The turn-on ton and turn-off toff delays of the OVD circuit depend on the OVD itself and the CMOS CL as well. (Switching the OVD output from low to high voltage is called "turning-on" and reverse switching is called "turning-off".)

Consider a piece of CMOS CL and its interaction with OVD circuit (Fig.11). The piece is an SPP including N logic gates. Each gate is shown symbolically as a connection of PMOS and NMOS networks. All the capacitances affecting ton and toff can be brought down

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